Pulse width modulators (PWMs) are a key circuit block in building power switching regulators. Conventional, analog technology pulse width modulator circuits must be adjusted to compensate for process-voltage-temperature (PVT) variations, while digital pulse width modulators offer much higher circuit precision tolerating wide PVT ranges. In addition, digital designs allow easy implementation of many circuit control functions, and are thus likely to be standard in future single-chip switcher designs.
Digital pulse with modulation is basically a digital controller pulse width generator where the system clock determined the pulse width accuracy and resolution. Very high system clock frequencies, greater than 100 mega-Hertz (MHz) are normally required to yield fine resolution. For instance, a 1.25 MHz, 7-bit pulse width modulator—having an 800 nanosecond (ns) pulse period with 128 resolution steps—requires a clock frequency of 160 MHz (1.25 MHz×128). This makes the design expensive and unsuitable for high-efficiency, low-power applications. To lower the clock frequency, a common practice involves utilizing a multiphase clocking scheme. However, such complex clocking systems generally result in various logic-timing problems.
To the extent that multi-phase clocking may be successfully employed for digital pulse width modulation by using a ring-oscillator, the minimum step size (highest resolution) possible is limited by the phase step of the ring-oscillator. However, when the targeted phase step is near or smaller than the physical delay of transistors, the design can become expensive and/or impractical to implement, a common resolution problem for digital pulse width modulator designs.
One traditional method to improve resolution is to use dithering. The minimum phase step size is employed while allowing several periods of digital pulse width modulator pulses to vary between two adjacent phase steps. Averaging in the power train inductive-capacitive (LC) filter smoothes the pulses so that values between the two adjacent phase steps can be realized as illustrated in FIG. 15. Where pulse durations of quarter modulations period are enabled (e.g. one-quarter, two-quarters, three-quarters, or one full period), a pulse length of, for example, 2.5 quarters is not possible without dithering. With dithering, however, not only are such pulse lengths possible (on an average basis) by extending every other pulse by one-quarter, but varying the density of dither pulses allows even finer resolutions such as 2.25 quarters on average to be achieved (by extending every fourth pulse in the example shown).
Dithering typically requires two circuit functions: a density generator receiving one or more input bits (normally assigned to the least significant bits of a state counter in the digital pulse width modulator) for dither control and producing a binary signal controlling the density functions of two adjacent digital pulse width modulator steps (i.e., PWM_State and PWM_State+1), where the density values are controlled by the input bit values; and a “Plus1” generator receiving the output of the density generator as an input and producing either a PWM_State code with a value PWM_State+1 for application to the inputs of a digital pulse width modulator converter or a “Plus1” pulse available at the output of the digital pulse width modulator converter, which output (PWM_State+1) is one resolution step wider than the normal pulse (PWM_State).
Traditional implementation methods for dithering circuits include a sequencer with pulse pattern lookup tables or density lookup tables followed by a “PWM_State+1” adder and registers. However, such implementations may not always operate satisfactorily with a digital pulse width modulator employing a fine-resolution edge extending approach to pulse modulation.
There is, therefore, a need in the art for an improved dithering circuit architecture.